Building integration plans, communicating status and priority among the teams (in/outside of SPE), assessing risks and developing mitigation plans Leading the project lifecycle in the SPE group, which starts at the requirements stage, through chip design and FW stages till SPE MP, including quality and yields improvement plans Responsible for bugs management prioritization and tracking and relevant knowledge transfer to the SPE group Working closely with development teams for environment improvements, such as automation, and driving mitigations to reduce risks Collaborating with PM for schedule tracking and modifications Evaluating new technologies and testing capabilities for improvement Working with the testing architecture team (DFT) to assure testing setups and coverage are met Engaging with a variety of teams: R&D, HW and SW, Chip design, Operations, thermal, signal integrity, FW and SW, layout, and more, Report project status for high level management
